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Low temperature crystallization of atomic-layer-deposited SrTiO3 films with an extremely low equivalent oxide thickness of sub-0.4 nm
Applied Surface Science ( IF 6.7 ) Pub Date : 2024-05-09 , DOI: 10.1016/j.apsusc.2024.160243
Hong Keun Chung , Jihoon Jeon , Han Kim , Myoungsu Jang , Sung-Chul Kim , Sung Ok Won , In-Hwan Baek , Yoon Jang Chung , Jeong Hwan Han , Sung Haeng Cho , Tae Joo Park , Seong Keun Kim

Despite SrTiO(STO) possessing a high dielectric constant, its application as a capacitor dielectric in dynamic random-access memory(DRAM) capacitors faces challenges due to the high-temperature annealing for crystallization, its compositional inhomogeneity, and the high leakage currents of STO films. To address these issues, we employ atomic layer deposition(ALD) of STO films onto Pt substrates at elevated temperatures(340–380 °C). The use of low-reactivity Pt electrodes effectively mitigates the initial growth of excess Sr, ensuring enhanced compositional uniformity along the film growth direction. Coupled with ALD at high temperatures, this approach facilitates the crystallization of STO films in the as-grown state, further enhancing the crystallinity with increasing film thickness. Subsequent low-temperature post-deposition annealing (PDA) at 400 and 500 °C achieves full crystallization. This process results in a remarkable increase in the dielectric constant, reaching approximately 150. Furthermore, the absence of microcracks after PDA, attributed to the formation of adequately dense films, contributes to substantially improved dielectric properties. Consequently, these STO films exhibit an exceptionally low equivalent oxide thickness of 0.34 nm coupled with an ultralow leakage current of 3.7 × 10 A/cm at an operation voltage of 0.8 V, promising for advancing DRAM capacitors. This study presents a pathway for the sustainable scaling of DRAMs, addressing challenges in ALD-grown STO films.

中文翻译:


原子层沉积 SrTiO3 薄膜的低温结晶,其等效氧化物厚度低于 0.4 nm



尽管SrTiO(STO)具有高介电常数,但由于结晶的高温退火、成分不均匀性以及STO的高漏电流,其作为动态随机存取存储器(DRAM)电容器中的电容器电介质的应用面临着挑战。电影。为了解决这些问题,我们在高温(340–380°C)下将 STO 薄膜原子层沉积 (ALD) 到 Pt 基底上。低反应性Pt电极的使用有效地减轻了过量Sr的初始生长,确保沿薄膜生长方向增强成分均匀性。与高温下的 ALD 相结合,这种方法促进了 STO 薄膜在生长状态下的结晶,随着薄膜厚度的增加,进一步提高了结晶度。随后在 400 和 500 °C 下进行低温沉积后退火 (PDA),实现完全结晶。该工艺导致介电常数显着增加,达到约 150。此外,由于形成了足够致密的薄膜,PDA 后不存在微裂纹,这有助于显着提高介电性能。因此,这些 STO 薄膜表现出 0.34 nm 的极低等效氧化物厚度,以及在 0.8 V 工作电压下 3.7 × 10 A/cm 的超低漏电流,有望用于先进的 DRAM 电容器。这项研究提出了一种可持续扩展 DRAM 的途径,解决了 ALD 生长的 STO 薄膜面临的挑战。
更新日期:2024-05-09
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