Rapid progress in the CMOS technology for the past 25 years has increased the vulnerability of processors towards faults. Subsequently, focus of computer architects shifted towards designing fault-tolerance methods for processor architectures. Concurrently, chip designers encountered high order challenges for designing fault tolerant processor architectures. For processor cores, redundancy-based fault tolerance methods for fault detection at core level, micro-architectural level ,thread level , and software level are discussed. Similar applicable redundancy-based fault tolerance methods for cache memory, and hardware accelerators are presented in the article. Recent trends in fault tolerant quantum computing and quantum error correction are also discussed. The classification of state-of-the-art techniques is presented in the survey would help the researchers to organize their work on established lines.

过去 25 年 CMOS 技术的快速进步增加了处理器出现故障的可能性。随后，计算机架构师的焦点转向为处理器架构设计容错方法。与此同时，芯片设计人员在设计容错处理器架构时遇到了重大挑战。对于处理器内核，讨论了基于冗余的内核级、微体系结构级、线程级和软件级故障检测的容错方法。本文提出了类似的适用于高速缓存和硬件加速器的基于冗余的容错方法。还讨论了容错量子计算和量子纠错的最新趋势。调查中提出的最先进技术的分类将有助于研究人员按照既定路线组织他们的工作。